Article information

2024 , Volume 29, ¹ 4, p.95-109

Giatsintov A.M., Mamrosenko K.A.

Testing graphics processing operations with graphics accelerator emulation

Nowadays, an increasing number of problems require the use of hardware accelerators to reduce the time required for calculations as well as for displaying their results. An important aspect of working with graphics operations is to achieve correctness for execution of operations and debugging of both subsystems and drivers involved in displaying of graphics information. This paper presents the architecture of an emulator of the graphics accelerator designed to diagnose and correct hard-to-detect errors within components of the graphics subsystem. Unlike the known solutions, the developed architecture allows using the emulator as a part of system emulators such as a QEMU and as an attached library for a driver of the graphics accelerator. The architecture of the developed emulator can be divided into several layers: the upper level provides API for application interaction with the emulator (initialization, programming of registers of the virtual device, etc.); the middle level performs service functions necessary for correct work of the emulator (memory management, thread pooling, checking if the emulated device has the requested register, etc.); the lower level performs emulation of a particular graphics chip. The virtual chip is controlled by reading and writing to the device registers — the emulator provides separate functions for these operations. One of the main advantages is the ability to run the graphics accelerator driver on a tool machine with capability for step-by-step debugging. The emulator allows detecting some intermittent errors that were hard to reproduce on real hardware.


Keywords: visualization, graphics system, rendering, operating system, emulation, QEMU

doi: 10.25743/ICT.2024.29.4.007

Author(s):
Giatsintov Alexander Michaylovich
PhD.
Position: Senior Research Scientist
Office: Federal State Institution Scientific Research Institute for System Analysis of the Russian Academy of Sciences
Address: 117218, Russia, Moscow, 36-1, Nakhimovsky prospect
E-mail: giatsintov@niisi.ras.ru
SPIN-code: 1359-4413

Mamrosenko Kirill Anatolievich
PhD.
Position: Director
Office: Federal State Institution Scientific Research Institute for System Analysis of the Russian Academy of Sciences
Address: 117218, Russia, Moscow, 36-1, Nakhimovsky prospect
E-mail: mamrosenko_k@niisi.ras.ru
SPIN-code: 5596-7877


Bibliography link:
Giatsintov A.M., Mamrosenko K.A. Testing graphics processing operations with graphics accelerator emulation // Computational technologies. 2024. V. 29. ¹ 4. P. 95-109
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